1. Field of the Invention
The present invention relates to a method for the processing of the defective elements in a memory made in integrated circuit form and comprising redundancy elements. It can be applied more particularly to the testers of such memories.
The greater the information storage capacity of a memory and the finer the integration technology, the greater is the degree to which these memories are liable to suffer manufacturing defects. Just one defect in a memory comprising a million cells will entail the discarding of this memory. Now, the trend in industry is towards constantly increasing the storage capacity and the degree of miniaturization.
2. Description of the Prior Art
To increase overall manufacturing efficiency, redundant memory networks have been used.
Thus, when a tester carries out the tests on integrated circuit wafers, if it detects one or more defective memory elements, then it will be able to replace them with redundant elements: the memory will then appear to be good on the whole and will not be discarded.
In this way, it is possible to recover memories comprising a limited number of defects.
It will be recalled that a memory is organized as a matrix of rows and columns. At each intersection of a column and a row, there is a cell that can be selected by means of the address of the column and the address of the row, the contents of this cell being read on the column.
The defects may relate to:
isolated memory cells, for example defects in the gate oxide of a cell; PA1 adjacent rows of cells, for example a short-circuit between two rows by residual filaments of poorly etched polycrystalline silicon; PA1 several rows of cells or several columns, for example, resulting from a poor contact inside a decoder used to designate an entire group of rows or an entire group of columns; PA1 two columns, for example resulting from a short-circuit by an aluminum bridge which sets up an abnormal connection between two lines of aluminum corresponding to two adjacent columns; PA1 etc. PA1 memorize the precise address of the defective column; PA1 deactivate the normal reading of the information elements coming from this column; PA1 read the information elements coming from a redundant column; PA1 bring these information elements to the reading amplifier of the defective column. PA1 1) For each defective element detected: PA1 searching for a first non-defective redundant element by the testing of the redundant elements of the memory, and PA1 assigning this first redundant element to the defective element; and PA1 2) When the tester has succeeded in assigning a redundant element to each defective element, replacing, in the memory, each defective element by the assigned redundant element.
The memory tester memorizes all the defects that appear during the testing of this memory to analyze them and determine the defective elements.
It must then connect the appropriate redundant elements, as replacements for the defective elements in such a way that the user of the memory has no particular constraint due to this replacement: it is said that the replacement must be transparent to the user who has access only to the external terminals of the integrated circuit.
For large-sized memories (comprising several hundreds of thousands of bits or more), the redundant elements will typically be whole rows of cells rather than individual cells, it being easier to replace rows in view of the constraints of the space occupied by circuits that need to be added so that the replacement is transparent to the user. However, certain defects, like short-circuits by aluminum bridges between two columns, can be replaced only through the replacement of these columns by other columns.
The replacing of a column is more difficult than that of a row. Indeed, when the memory is organized in words of several bits, a memory address then designates, firstly, a single determined row and, secondly, a number of columns equal to the number of bits.
The replacement of a defective column can be done by routing to a redundant column instead of to a defective column. A very cumbersome circuitry is then needed to:
A similar circuitry must be designed for the writing of information elements in the redundant column.
Another way of replacing a defective column consists in making provision, for example in a memory organized in 8-bit words, for a group of eight redundant columns designed to replace a group of eight columns, at least one of which is defective. In other words, if a memory address designates eight columns and if the tester detects a defect in at least one of these eight columns, it replaces the entire group of eight columns designated by this address by a group of eight redundant columns.
Other approaches are possible and the choice of any one of them depends on the structure of the memory, the constraints of the space occupied by the necessary circuitry and the desired repairing capacity.
Hereinafter, the term "defective element" of a given memory shall be understood to mean the smallest structure of rows or columns of this memory that can be repaired by a redundant element of a same structure of rows or columns.
It may therefore be a single row or column, or a set of rows or columns, at least one of which is defective.
It will be noted that certain memories implement only one type of redundancy, for example column redundancy.
It is the tester, when it has been able to prepare a list of the defective elements of a given memory, that implements the repairing of this memory: it replaces each defective element by a redundant element.
Generally, in the memorizing elements of a memory, it records one information element identifying the defective element and one information element identifying the redundant element that replaces it.
These memorizing elements may be a memory network or a battery of fuses, and constitute the redundancy activation table of the memory.
It is this table that makes it possible, during the subsequent functioning of the memory, to select the redundancy element corresponding to a defective element, the address of which is presented to the input of the memory.
After each repair of a defective element, the tester applies the defect detection test to this repaired defective element. This test consists chiefly in verifying that an information element read is truly the one that has been written earlier. If the test is positive, the memory is good. If it is negative, i.e. if at least one defect is found, the memory is discarded. (It is not possible to repair a defective element that has already been repaired, i.e. one that has already been replaced by a redundancy element: the repair is generally irreversible.)
Furthermore, it is generally preferred to repair first of all the column elements before the row elements for it is the column elements that statistically produce the greatest number of defects.
Now, assuming that a row is highly defective, the defective columns being repaired first, it is highly probable that the repaired columns will always appear to be defective and that the memory will be discarded, while the defects detected on the repaired columns may come from the highly defective row that has not yet been repaired.
Indeed, it will be recalled that the redundant columns are placed on the continuation of the rows of the memory map, and the redundant rows on the columns of the memory plane.